SER Analysis of Multiple Transient Faults in Combinational Logic

In the VLSI field, reliability of chips is a major issue and it becomes more significant considering the continuous technology down-scaling. Modern chips are extremely sensitive to various factors such as radiation and, thus, it is crucial to implement tools for the evaluation of their vulnerability to the aforementioned hazards. We present a Soft Error Rate estimation methodology for sequential circuits, based on Monte-Carlo simulations and taking into account Multiple Event Transients. Our tool incorporates the masking effects in order to quantify the number of transients that will be latched from the sequential elements. The verification with HSPICE shows a deviation of about 10%.