Aging-Aware Coding Scheme For Memory Arrays

The reliability of digital integrated circuits is becoming the primary design concern in advanced technology nodes. The accelerated transistor aging mechanisms, such as Bias Temperature Instability, reduce the noise margin of memory cells leading to increased failure rate. Traditionally, error correction codes, such as Hamming code, are widely used to detect and correct transient errors in memory arrays, due to radiation-induced soft errors. In this work, we propose a new coding scheme which is able to reduce the overall aging rate of the memory arrays, by balancing the signal probabilities of the stored values. The optimal coding scheme is found with the help of an optimization technique which evolves a systematic Hamming code into an aging-aware non-systematic code. This technique is applicable to different memory arrays such as caches. The simulation results on different workloads show 45.2% reduction in aging induced Static Noise Margin (SNM) degradation compared to the conventional methods.