A Fully Parallel Content Addressable Memory Design Using Multi-Bank Structure

This paper presents a novel technique to reduce the power and latency in content-addressable memories (CAMs). The first technique is to discontinue the unnecessarily subsequent search-line precharge process based on pipelined match-line searching operation. Speed is improved significantly since search-line registers are comparing in parallel. Meanwhile, the power consumption is also significantly reduced by disabling the subsequential match-line and search-line precharge process. The second technique is to improve the speed further by implementing split-path match-line circuit into each match-line segment. Without additional complex peripheral circuits, our proposed design can achieve up to 47.78% reduction in power consumption. At the same time, 95.4% time can be shrunk as compared to Conventional NOR-type Architecture CAM design.