Design of high-speed low-power polar BP decoder using emerging technologies

With the provable asymptotically optimal property in the sense of channel capacity, polar codes have emerged as one of the potential channel code candidates for the next-generation wireless communication systems. To date, numerous works have been reported on VLSI implementation of polar decoders. However, the efficient hardware design of polar decoders that can be used in the real-time energy-constraint mobile devices is still a huge challenge. This paper, for the first time, investigates high-speed low-power polar decoder design using FinFET and near-threshold computing (NTC) technologies. Specifically, the hardware performance of polar decoder with belief propagation (BP) decoding approach is studied and evaluated. Synthesis results show that the joint use of these two emerging technologies can lead to significant reduction in both power consumption and decoding delay at the same time.