Digital Low-Dropout Regulator With Anti Pvt-Variation Technique For Dynamic Voltage Scaling And Adaptive Voltage Scaling Multicore Processor

Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the V OUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔV OUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔV OUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔV OUT , while T ranges from 0–80°C and V OUT ranges from 0.6–1V in steady state, and the transient response time is 1.3µs in case of a load step from 1mA to 201mA.