28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter.

The successive approximation register (SAR) ADC is the most energy efficient architecture with moderate conversion rate and resolution. However, its comparator noise limits its resolution without sacrificing power efficiency. The delta-sigma modulator (DSM) is the most popular architecture for achieving high SNDR due to its oversampling, but the bulky operational amplifier (op-amp) makes it area inefficient. In LTE Advanced, the bandwidth (BW) of downlink ADCs needs to be configured according to the number of inter-band non-contiguous carrier aggregation (NCCA), which motivates us to combine the benefits of both architectures to reduce area and power consumption simultaneously with high SNDR. The noise-shaping SAR ADC [1] suppresses the comparison and quantization noise in signal BW using a simple cascaded FIR-IIR filter, which obviates the need for a power-hungry low-noise comparator or high-performance op-amp. To some extent, the noise-shaping SAR ADC is a hybrid of DSM and SAR ADCs. Hence, it has the potential to achieve the high resolution and good power efficiency of DSM and SAR ADCs, respectively. However, the passive sampling in an FIR filter introduces considerable thermal noise to the ADC, making it difficult to achieve a high SNR. This work presents an energy-efficient noise-shaping SAR ADC that uses a gain-enhanced dynamic amplifier and some capacitors to construct a low-noise dynamic FIR-IIR filter. The prototype achieves a peak SNDR of 79.74dB over a 5MHz BW with a power consumption of 0.46mW from a 1V supply.