A 45-75mhz 197-452 Mu W Oscilator With 164.6db Fom And 2.3ps(Rms) Period Jitter In 65nm Cmos

This paper presents a novel oscillator architecture that uses a low frequency temperature stable clock generated by a low power RC relaxation oscillator to improve the temperature stability of a low noise ring oscillator. Fabricated in 65nm CMOS process, the prototype oscillator consumes 197 to 452 mu W across an output frequency range of 45-to-75MHz. At 70MHz, the measured period jitter is 2.3ps(rms) with phase noise of -104dBc/Hz at 100kHz offset, which translates to an FoM of 164.6dB.