Performance optimization in FinFET-based circuit using TILOS-like gate sizing

Continuous scaling of CMOS technology suffers from severe leakage current. Fin-type field effect transistor (FinFET) is an alternative to overcome scaling challenge. The shift from 2D planar to 3D transistors enables greater density, lower power consumption, and higher performance. The delay/power optimization framework for FinFET based circuit using TILOS-like gate sizing is presented in this paper. Utilizing unique feature of FinFET based circuit. The TILOS-like sizing algorithm is used to optimize delay and power in 3D FinFET circuit. The proposed method considers three operating modes of FinFET logic gate for optimization. The ISCAS85 benchmark circuit with 32nm FinFET PTM model is applied to verify our method. In the experiment the power of the tested circuit is reduced by 12.99% in average while minimizing delay.