Exploiting FPGAs from Higher Level Languages A Signal Analysis Case Study

2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)(2017)

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Field Programmable Gate Arrays (FPGAs) are usually perceived as difficult to exploit due to the High Level of expertise required to program them. In the last years, the major FPGAs vendors have produced different High Level Synthesis (HLS) tools to help programmers during the flow of acceleration of their algorithms through the hardware architecture. However, these tools often use languages considered low level from the point of view of data scientists and are still much too difficult to use for software developers. This complexity limits their usage in a number of fields, from data science to signal processing, where the computational power offered by FPGAs could be highly beneficial. One way to overcome this problem is to realize libraries of widely used algorithms that transparently offload the computation to the FPGAs device from modern High Level Languages. Our work presents an interface between R, a language commonly used by statisticians and data scientists, and an FPGA connected via PCI-Express (PCIe). We use the Reusable Integration Framework for FPGA Accelerators (RIFFA) to send and receive data from PCIe connection. To showcase the use of the described interface and the improvements given by making use of FPGAs in signal analysis applications we used Xilinx Vivado Design Suite to implement an accelerated and optimized version of the Autocorrelation Function (ACF) present in the default libraries used by R.
FPGAs,higher level languages,signal analysis,field programmable gate arrays,high level synthesis,HLS tools,hardware architecture,software developers,data science,signal processing,computational power,PCI-express,PCIe,reusable integration framework for FPGA accelerators,RIFFA,Xilinx Vivado Design Suite,autocorrelation function,ACF
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