Performance investigation on BCH codec implementations
2016 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)(2016)
摘要
This paper investigates the performance of the BCH encoder and decoder for different error-correcting capabilities. The focus is on BCH codes of length 255. The motivation for this research is a project where data symbols of this length are transmitted over an error-prone wireless channel. The paper presents a mathematical introduction into encoding for cyclic codes and decoding of the BCH code. The code was implemented in both software and hardware and the performance and cost of both implementations were measured for different code parameters.
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关键词
BCH,forward error correction,FPGA,ASIC,performance
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