Regularized Logistic Regression For Fast Importance Sampling Based Sram Yield Analysis
PROCEEDINGS OF THE EIGHTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED)(2017)
摘要
In this paper, we propose a fast logistic regression based importance sampling methodology with ordered feature selection to avoid overfitting and enable regularization. We rely on the importance region search simulations to build a regularized logistic regression model that is capable of accurately predicting pass fail criteria for purposes of yield analysis stage. We also propose a cross-validation-based regularization framework for ordered feature selection. We prove the efficiency of the proposed methodology by analyzing state-of-the-art FinFET SRAM designs. The proposed methodology is comprehensive and computationally efficient resulting in high-fidelity models. We report on average around 4.5% false prediction rate for the importance sample points prediction. This translates into accurate yield prediction for the rare fail events. All this comes at significant savings in runtime.
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关键词
Integrated circuit design,logistic regression,yield,SRAM cells,sparse regression
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