Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning

ISPD, pp. 15-21, 2017.

Cited by: 30|Views130
EI

Abstract:

Design rule check (DRC) violations after detailed routing prevent a design from being taped out. To solve this problem, state-of-the-art commercial EDA tools global-route the design to produce a global-route congestion map; this map is used by the placer to optimize the placement of the design to reduce detailed-route DRC violations. Howe...More

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