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Towards SMT-based LTL model checking of clock constraint specification language for real-time and embedded systems.
LCTES, no. 5 (2017): 61-70
The Clock Constraint Specification Language (CCSL) is a formal language companion to MARTE (shorthand for Modeling and Analysis of Real-Time and Embedded systems), a UML profile used to facilitate the design and analysis of real-time and embedded systems. CCSL is proposed to specify constraints on the occurrences of events in systems. How...More
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