Incremental Layer Assignment for Timing Optimization
ACM Trans. Design Autom. Electr. Syst., Volume 22, Issue 4, 2017, Pages 75:1-75:25.
DesignAlgorithmsPerformanceLayer assignmentcritical path timingMore(1+)
With VLSI technology nodes scaling into the nanometer regime, interconnect delay plays an increasingly critical role in timing. For layer assignment, most works deal with via counts or total net delays, ignoring critical paths of each net and resulting in potential timing issues. In this article, we propose an incremental layer assignment...More
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