FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency.

Jie Guo,Wujie Wen,Jingtong Hu,Danghui Wang,Hai Helen Li,Yiran Chen

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems（2017）

引用 17|浏览64

暂无评分

摘要

Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction capability. However, to achieve better perf...

查看译文

关键词

Parity check codes,Error correction codes,Bit error rate,Sensors,Interference,Reliability,Logic gates

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要