A quantitative design methodology for high-speed interpolation/averaging ADCs.

This paper proposes a new quantitative and systematic design methodology for high-speed interpolation/ averaging ADCs. The methodology consists of a new mathematical BW/gain model derived from the pre-amps arrays static model and new small-signal model, a new offset modeling mechanism that can accurately estimate and help to reduce the offset, and hence a new systematic design flow. The methodology enables a quantitative and systematic analysis, conducts iterative and accurate calculation realized in MATLAB, and finally leads to an optimized ADC design that reaches a guaranteed optimum full-chip performance with given specs (i.e., resolution, speed, input range, power, input CM, etc.). The methodology shows significant advantage over the traditional trial-and-error ADC design approach with respect to performance and design efficiency, and is much more reliable in nanometer technologies. The proposed methodology was fully validated in silicon: a 4-bit 5GSps interpolation/averaging ADC is fabricated in a 65nm CMOS technology and the measurement results show that our ADC has indeed achieved an outstanding and comparable overall performance compared to reported state-of-the art ADCs.