An Hdl-Synthesized Injection-Locked Pll Using Lc-Based Dco For On-Chip Clock Generation

This paper presents an HDL-synthesized injectionlocked phase-locked loop using LC-based DCO for on-chip clock generation. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm CMOS process, this prototype demonstrates a 0.142ps integrated jitter at 3.0GHz and consumes 4.6mW while only occupying an area of 0.12mm(2). It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL up-to-date.