Enabling the high level synthesis of data analytics accelerators.
CODES+ISSS(2016)
摘要
Conventional High Level Synthesis (HLS) tools mainly target compute intensive kernels typical of digital signal processing applications. We are developing techniques and architectural templates to enable HLS of data analytics applications. These applications are memory intensive, present fine-grained, unpredictable data accesses, and irregular, dynamic task parallelism. We discuss an architectural template based around a distributed controller to efficiently exploit thread level parallelism. We present a memory interface that supports parallel memory subsystems and enables implementing atomic memory operations. We introduce a dynamic task scheduling approach to efficiently execute heavily unbalanced workload. The templates are validated by synthesizing queries from the Lehigh University Benchmark (LUBM), a well know SPARQL benchmark.
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关键词
data analytic accelerators,conventional high level synthesis tools,HLS,compute intensive kernels,digital signal processing applications,data analytic applications,unpredictable data accesses,dynamic task parallelism,thread level parallelism,parallel memory subsystems,dynamic task scheduling approach,Lehigh University Benchmark,SPARQL benchmark,LUBM
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