A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme.

The measured H-field EMI peak was reduced by around 15dB in a 4-wire single-ended DRAM interface by using a 3-level balanced coding scheme with a 100% pin efficiency. Charge-pump circuits are used to generate 3-level channel signals (-100mV, 0, +100mV) at TX. The RX input comparator uses the ground-level (0) as the voltage reference and employs the meta-stability to identify the ground-level input. The energy efficiency was 2.67pJ/b at 6.4Gb/s with a 65nm LP 1.2V CMOS process and 3-inch FR-4.