A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating. Z. Chen, S. H. Kulkarni,V. E. Dorgan, U. Bhattacharya,K. ZhangVLSI Circuits（2016）引用 23|浏览4暂无评分AI 理解论文溯源树样例生成溯源树，研究论文发展脉络Chat Paper正在生成论文摘要
