np-ECC: Nonadjacent position error correction code for racetrack memory

Racetrack memory is a promising non-volatile memory because of its ultra-high storage density. The data are stored along the tape-like cell, where a “shift” operation is used to move the data in a cell back and forth to be accessed. Shift operations suffer from “position error”, where the shift distance is incorrect. Previous work solved the error by position error correction code (p-ECC). However, a bit error within the p-ECC bits will fail the correction mechanism. To protect p-ECC bits from bit errors, we propose a new mapping method for p-ECC, called nonadjacent position error correction code (np-ECC) in this paper. Evaluation shows significant reduction on correction mechanism failure rate.