Verilog-A compact model of integrated tapered spiral inductors

This paper presents a Verilog-A compact model for integrated spiral inductors. The implemented model takes into consideration the geometric parameters characterizing the inductor layout, as well as the technological parameters. The accuracy of the model is checked against simulations with ASITIC simulator and limitations of the model are established. The model is integrated into Cadence environment, offering the designer the possibility to obtain the inductor design using the optimization tools. Moreover, simulation of radio frequency blocks such as voltage controlled oscillators, considering the non-idealities of both the inductor and the transistors in deep-submicron technologies is offered to the designers.