A Low Power Pipelined Adc With Improved Mdac

The design of a low power 16-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. The area of sampling capacitor and the chip is reduced by adopting stage scaling technology and optimizing the structure of multiply digital-to-analog converter (MDAC). Low power dissipation and high performance operational trans-conductance amplifiers (OTA) in the first two pipelined stages are realized by using dynamic biasing technology. This work is implemented in 0.18 mu m mixture signal CMOS process with a 1.8V power supply. The pipelined ADC exhibits 91.9dB SFDR and 74.2dB SNDR, consuming 210mW with 5MHz differential input signal at 100MS/s.