UTPlaceF: a routability-driven FPGA placer with physical and congestion aware packing.
IEEE Trans. on CAD of Integrated Circuits and Systems(2018)
摘要
FPGA packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose a FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routablity. A novel physical and congestion aware packing alogrithm and several congestion aware detailed placement techniques are proposed. Compared with the top 3 winners of ISPD'16 FPGA placement contest, UTPlaceF can achieve 3.3%, 7.7% and 28.3% better routed wirelength with similar or shorter runtime.
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关键词
Field programmable gate arrays,Table lookup,Routing,Digital signal processing,Random access memory,Pins
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