A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

Giuseppe Natale
Giuseppe Natale
Giulio Stramondo
Giulio Stramondo
Pietro Bressana
Pietro Bressana

ICCAD, 2016.

Cited by: 23|Bibtex|Views19|Links
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Abstract:

Iterative Stencil Loops (ISLs) are a specific class of algorithms of great importance for their substantial presence in a lot of industrial and scientific computing applications, such as in numerical methods for solving partial differential equation -- e.g. reverse time migration and heat distribution simulation --- or in cellular automat...More

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