MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1237-1250, 2018.
As very large-scale integration technology shrinks to fewer tracks per standard cell, e.g., from 10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multibit flip-flops or flop t...More
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