MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems(2018)

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摘要
As very large-scale integration technology shrinks to fewer tracks per standard cell, e.g., from 10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multibit flip-flops or flop trays to save power creates large cells that further complica...
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关键词
Pins,Standards,Optimization,Rails,Layout,Very large scale integration,Measurement
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