Routing-Aware Incremental Timing-Driven Placement

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)(2016)

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摘要
Meeting timing requirements and improving routability are becoming more challenging in modern design technologies. Most timing-driven placement approaches ignore routability concerns which may lead to a gap in routing quality between the actual routing and what is expected. In this paper, we propose a routing-aware incremental timing-driven placementtechnique to reduce early and late negative slacks while considering global routing congestion. Our proposed flow considers both timing and routing metrics during the detailed placement. We also presents a comprehensive analysis of timing quality score and the total number of routing overflows and the trade-off between them by modifying the International Conference on Computer Aided Design (ICCAD) 2015 timing-driven contest benchmarksand the displacement constraints. Experimental results on the ICCAD 2015 Incremental Timing-Driven Contest benchmarks show the efficacy of our proposed routing-aware incremental timing-driven placement method. On average, we obtain 22% and 17% improvement in timing quality score and global routing overflows, respectively, compared to the first placed team at 2015 ICCAD contest.
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关键词
Timing-driven Placement,Routing-aware Placement
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