ILP-based modulo scheduling for high-level synthesis
CASES, pp. 1:1-1:10, 2016.
In high-level synthesis, loop pipelining is a technique to improve the throughput and utilisation of hardware datapaths by starting new loop iterations after a fixed amount of time, called the initiation interval (II), allowing to overlap subsequent iterations. The problem is to find the smallest II and corresponding operation schedule th...More
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