A 25gb/S 3d-Integrated Silicon Photonics Receiver In 65nm Cmos And Pic25g For 100gbe Optical Links

A 25Gb/s silicon photonics receiver comprising an Electronic Integrated Circuit and a Photonic Integrated Circuit fabricated in 65nm CMOS and in PIC25G technologies respectively is presented. The two chips are 3D-integrated using copper pillars. The front-end amplifier introduces low-noise techniques, realizing record-low input-referred noise current of 0.91 mu Arms, leading to the highest sensitivity (OMA = -11.3dBm) among 25Gb/s silicon photonics receivers reported to date.