A 28nm Fd-Soi Standard Cell 0.6-1.2v Open-Loop Frequency Multiplier For Low Power Soc Clocking

Martin Cochet,Sylvain Clerc,Mehdi Naceur,Pierre Schamberger,Damien Croain,Jean-Luc Autran,Philipe Roche

2016 IEEE International Symposium on Circuits and Systems (ISCAS)（2016）

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摘要

This paper presents a new design for SoC clocking based on open-loop frequency multiplication. The architecture, fully implemented in 28nm FD-SOI standard cells, achieves frequency tracking within one input reference period making it a promising candidate for Dynamic Voltage and Frequency Scaling (DVFS) schemes. A calibration scheme is implemented for wide voltage range (0.6-1.2V) operation and to offset P&R and variability induced mismatch. Measurements at 0.6V (0.8/0.4V FBB) show a Fmax of 93MHz with a power of 2.91mW/MHz and a jitter of 2.7 % UI.

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关键词

calibration scheme,DVFS schemes,dynamic voltage and frequency scaling schemes,frequency tracking,open-loop frequency multiplication,SoC clocking design,low power SoC clocking,open-loop frequency multiplier,FD-SOI standard cell,size 28 nm,voltage 0.6 V to 1.2 V,frequency 93 MHz

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