An In-Depth Study Of Next Generation Interface For Emerging Non-Volatile Memories

Non-Volatile Memory Express (NVMe) is designed with the goal of unlocking the potential of low-latency, random-access, memory-based storage devices. Specifically, NVMe employs various rich communication and queuing mechanism that can ideally schedule four billion I/O instructions for a single storage device. To explore NVMe with assorted user scenarios, we model diverse interface-level design parameters such as PCI Express, NVMe protocol, and different rich queuing mechanisms by considering a wide spectrum of host-level system configurations. In this work, we also assemble a comprehensive memory stack with different types of emerging NVM technologies, which can give us detailed NVMe related statistics like I/O request lifespans and I/O thread-related parallelism.Our evaluation results reveal that, i) while NVMe handshaking is light-weight for flash memory that uses block-based accesses (Block NVM), it can impose tremendous overheads for memristor technology (DRAM-like NVM), ii) in contrast to the common expectation, the performance of an NVMe-equipped system may not improve in a scalable fashion as the queue depth and the number of queues increase, and iii) more- and deeper-queue systems atop a Block NVM can significantly suffer from tremendous host-side memory requirements, whereas a DRAM-like NVM can cause frequent system stalls due to NVMe's inefficient interrupt service routine.