An FPGA Architecture to Accelerate the Burrows Wheeler Transform by Using a Linear Sorter

    IPDPS Workshops, pp. 156-161, 2016.

    Cited by: 3|Bibtex|Views1|Links
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    Abstract:

    The Burrows-Wheeler Transform (BWT) has been used in several applications demanding high volumeof data and real-time capabilities. Current research focuses onreducing the time to compute the BWT by software or hardwaremeans. This paper presents a novel FPGA architecture basedon a Linear Sorter (LS) to efficiently calculate the BWT. Thearc...More

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