Incremental layer assignment for critical path timing

DAC, pp. 85:1-85:6, 2016.

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Abstract:

With VLSI technology nodes scaling into nanometer regime, interconnect delay plays an increasingly critical role in timing. For layer assignment, most works deal with via counts or total net delays, ignoring critical paths of each net and resulting in potential timing issues. In this paper we propose an incremental layer assignment framew...More

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