A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider.
IEEE Journal of Solid-State Circuits(2016)
摘要
Phase noise performance of ring oscillator based digital fractional-N phase-locked loops (FNPLLs) is severely compromised by conflicting bandwidth requirements to simultaneously suppress oscillator phase and quantization noise introduced by the time-to-digital converter (TDC), ΔΣ fractional divider, and digital-to-analog converter (DAC). As a consequence, their figure-of-merit (FoMJ) that quantifi...
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关键词
Phase noise,Phase locked loops,Quantization (signal),Voltage-controlled oscillators,Jitter,Bandwidth,Clocks
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