Technique for Increasing the Output Impedance of CMOS Regulated Cascode Circuits.

A technique is proposed for the design of a modified CMOS regulated cascode having an output impedance significantly greater than that of a conventional regulated cascode. Simulation results for an illustrative design, operating at 10 mu A from a 1V supply, show an increase in output resistance from 636 M Omega and output bandwidth of 55 kHz for a conventional circuit to 6.68 G Omega and 389 kHz, respectively, for the proposed design.