A Fractional-N Counter-Assisted DPLL With Parallel Sampling ILFD.

A fractional-N digital phase-locked loop (DPLL) with ring oscillator based injection-locked frequency divider (ILFD) and parallel sampling phase samplers is presented. The ILFD utilizes dual path injection technique to achieve wide locking range (4.2-23 GHz) and low power consumption. A low-power parallel sampling phase sampler based time-to-digital converter (TDC), which achieves sub-gate-delay r...