A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique.
IEEE Transactions on Circuits and Systems I: Regular Papers(2016)
摘要
A 12-bit 210-MS/s 2-channel time-interleaved analog-to-digital converter (ADC) employing a pipelined-SAR architecture for low-power and high-speed application is presented. The proposed ADC is partitioned into 3 stages with a passive residue transfer technique between the 1st and 2nd stages for power saving and active residue amplification between the 2nd and 3rd stages for noise consideration. Fu...
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关键词
Capacitors,Switches,Capacitance,Calibration,Linearity,Analog-digital conversion,CMOS integrated circuits
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