A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution

Takushi Hashida,Yasumoto Tomita,Yuuki Ogata,Kosuke Suzuki, Shigeto Suzuki,Takanori Nakao, Yuji Terao, Satofumi Honda,Sota Sakabayashi,Ryuichi Nishiyama,Akihiko Konmoto,Yoshitomo Ozeki,Hiroyuki Adachi,Hisakatsu Yamaguchi,Yoichi Koyanagi,Hirotaka Tamura

VLSIC（2014）

引用 2|浏览24

暂无评分

摘要

A 36-Gbps transceiver with a continuous-time linear equalizer and a 1-tap DFE in 20-nm CMOS is demonstrated. The transceiver uses a quarter-rate (i.e., 9-GHz) differential-clock distribution to reduce the clock-delivery power. Multi-phase half-rate clock signals that drive the transceiver front-ends are generated by a delay-locked loop and frequency doublers that systematically reduce the impact of skew and jitter. The transceiver occupies 0.55 mm2 and consumes 609.9 mW of power from a 0.9-V supply.

查看译文

关键词

CMOS analogue integrated circuits,MMIC frequency convertors,clock distribution networks,decision feedback equalisers,delay lock loops,field effect MMIC,frequency multipliers,radio transceivers,1-tap DFE,bit rate 36 Gbit/s,clock-delivery power,continuous-time linear equalizer,delay-locked loop,frequency 9 GHz,frequency doublers,jitter,multiphase half-rate clock signals,power 609.9 mW,quarter-rate clock distribution,size 20 nm,skew,transceiver front-ends,voltage 0.9 V,

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要