On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs

Joshua Liang,Mohammad Sadegh Jalali,Ali Sheikholeslami,Masaya Kibune,Hirotaka Tamura

VLSIC（2014）

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摘要

On-chip jitter measurement is demonstrated in a 10Gb/s CDR by correlating the phase detector outputs of two adjacent CDR lanes. The RMS jitter of the received data and an estimate of the jitter's power spectral density are then extracted without using an external reference clock. Circuits implemented in 65nm CMOS measure random jitter ranging from 0.85ps to 1.89ps in PRBS31 data with no more than 100fs error compared to an 80GS/s real-time oscilloscope. Sinusoidal jitter of 0.89ps to 5.1ps is measured with a worst-case error of 580fS compared to the oscilloscope.

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关键词

CMOS integrated circuits,clock and data recovery circuits,jitter,oscilloscopes,phase detectors,CMOS technology,PRBS31 data,RMS jitter,adjacent CDR lane,bit rate 10 Gbit/s,external reference clock,multilane CDR,on-chip data jitter measurement,oscilloscope,phase detector output,power spectral density,size 65 nm,subpicosecond accuracy,time 0.85 ps to 1.89 ps,time 0.89 ps to 5.1 ps,

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