56gb/S Pam4 And Nrz Serdes Transceivers In 40nm Cmos

2015 Symposium on VLSI Circuits (VLSI Circuits)（2015）

引用 11|浏览14

暂无评分

摘要

This paper presents 56Gb/s PAM4 and NRZ SerDes transceivers (TRXs), designed and fabricated in advance CMOS technology. Incorporating broadband techniques, noise suppression skills, and clock extraction circuits, this work demonstrates feasibility of 56Gb/s SerDes and compares tradeoffs between the two data format.

查看译文

关键词

PAM4,NRZ,SerDes transceiver,serializer-deserializer transceiver,CMOS integrated circuit,broadband technique,noise suppression,clock extraction circuits,bit rate 56 Gbit/s,size 40 nm

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要