An Incremental Timing-Driven Flow Using Quadratic Formulation For Detailed Placement

2015 IFIP/IEEE INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC)(2015)

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摘要
In this work, we present a flow for the Incremental Timing-Driven Placement problem. Given a legal placement, the aim is to reduce the circuit's timing violations without changing significantly the cell density, subject to a maximum displacement constraint. Our flow consists of two core steps: useful clock skew optimization and critical path fine tuning. During useful clock skew optimization, sequential cells are replaced, seeking to minimize clock skew. After that, a quadratic formulation is used to further reduce critical path delays. An incremental legalization tool is also presented, which supports the methods developed in this work. Our Incremental Timing-Driven Placement flow can achieve, on average, 0.3%, 26.2%, 8.7% and 23.7% of the normalized quality score improvement compared to state-of-the-art algorithms.
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关键词
Timing Optimization,Detailed Placement,Quadratic Placement,Legalization
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