Power and area reduction in multi-stage addition using operand segmentation
VLSI-DAT, pp. 1-4, 2013.
This paper presents an architectural technique to efficiently implement multi-stage additions through operand segmentation. Carry bypass is leveraged to break the dependency between the two segmented adders, reducing the delay of the critical path. This allows for power- and area-efficient hardware implementation due to the increased timi...More
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