On the Algorithmic Aspects of Using OpenMP Synchronization Mechanisms II: User-Guided Speculative Locks.

In this paper we continue our investigations started in [8] into the effects of using different synchronization mechanisms in OpenMP-threaded iterative mesh optimization algorithms. We port our test code to the Intel (R) Xeon (R) processor (former codename "Haswell") by employing a user-guided locking API for OpenMP [4] that provides a general and unified user interface and runtime framework. Since the Intel Transactional Synchronization Extensions (TSX) provide two different options for speculation - Hardware Lock Elision (HLE) and Restricted Transactional Memory (RTM) - we compare a total of four different run modes: (i) HLE, (ii) RTM, (iii) OpenMP critical, and (iv) "unsynchronized". As we did in [8], we find that either speculative execution option always outperforms the other two modes in terms of their convergence characteristics. Even with their higher overhead, the TSX options are very competitive when it comes to runtime performance measured with the "time-to-convergence" criterion introduced in [8].