TILA: Timing-Driven Incremental Layer Assignment
International Conference on Computer-Aided Design, pp. 110-117, 2015.
As VLSI technology scales to deep submicron and beyond, interconnect delay greatly limits the circuit performance. The traditional 2D global routing and subsequent net by net assignment of available empty tracks on various layers lacks a global view for timing optimization. To overcome the limitation, this paper presents a timing driven i...More
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