Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems
IPDPS Workshops, 2015.
Within this paper we present a floor planner for partially-reconfigurable FPGAs that allow the designer to consider bit stream relocation constraints during the design of the system. The presented approach is an extension of our previous work on floor planning based on a Mixed-Integer Linear Programming (MILP) formulation, thus allowing t...More
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