Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis
2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)(2016)
摘要
High-level synthesis (HLS) promises high-quality hardware with minimal development effort. In this paper, we evaluate the current state-of-the-art in HLS and design techniques based on software references and architecture references. We present a software reference study developing a JPEG encoder from pre-existing software, and an architecture reference study developing an AES block encryption module from scratch in SystemC and SystemVerilog based on a desired architecture. Additionally, we develop micro-benchmarks to demonstrate best-practices in C coding styles that produce high-quality hardware with minimal development effort. Finally, we suggest language, tool, and methodology improvements to improve upon the current state-of-the-art in HLS.
更多查看译文
关键词
high-quality hardware design,development effort budget,high-level synthesis,HLS,software references,architecture references,JPEG encoder,AES block encryption module,SystemC,SystemVerilog,C coding styles
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络