Design and allocation of loosely coupled multi-bit flip-flops for power reduction in post-placement optimization

    Hyoungseok Moon
    Hyoungseok Moon

    ASP-DAC, pp. 268-273, 2016.

    Cited by: 9|Bibtex|Views1|Links
    EI

    Abstract:

    Merging 1-bit flip-flops into multi-bit flip-flops in the post-placement stage is one of the most effective techniques for minimizing clock power. The obstacles that hinder the merging process for multi-bit flip-flops are (1) the input and output timing constraint on every flip-flop, (2) the area constraint on every partitioned bin in the...More

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