Automatic FPGA system and interconnect construction with multicast and customizable topology

Modern FPGA system integration tools, such as Qsys and Vivado, seek to help designers easily instantiate and connect IP cores. These tools require the cores to ascribe to a specific interconnect abstraction, which is either a high-level memory-mapped or low-level point-to-point streaming protocol. We present a system-level construction tool that gives the designer more control over the nature of the interconnect - specifically permitting multicast communication and the ability to easily construct custom network topologies. Our tool requires less user input than Qsys and yields a 5% area savings and 35% reduction in simulated execution time for a large and complex linear algebra application. The primary goal of this work is to make the designer's job easier by automating the design of interconnect, including exploration of alternative structures and communication patterns.