Optimized high-level synthesis of SMT multi-threaded hardware accelerators

FPT, pp. 176-183, 2015.

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Abstract:

Recent high-level synthesis tools offer the capability to generate multi-threaded micro-architectures to hide memory access latencies. In many HLS flows, this is often achieved by just creating multiple processing element-instances (one for each thread). However, more advanced compilers can synthesize hardware in a spatial form of the bar...More

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