Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR

In this work, the optimum design of Trigate-on-Insulator MOSFET devices is investigated with the MASTAR platform, focusing on the channel aspect ratio. First, the MASTAR Trigate model is described, and new components are validated with TCAD simulations. Using the verilog-A implementation of this model, SPICE simulations of inverter chains are later performed to analyze the device performance, employing different power reduction techniques. Finally, the variability issue is addressed with Monte-Carlo simulations of 6T SRAM cells.